The present invention generally relates to semiconductor devices, and more particularly, to structures, fabrication methods, and design structures associated with active and passive fin-based devices.
A fin metal-oxide-semiconductor field effect transistor (finMOSFET, or finFET) may provide solutions to metal-oxide-semiconductor field effect transistor (MOSFET) scaling problems at and below, for example, the 22 nanometer (nm) node of semiconductor technology. A finFET includes at least one narrow semiconductor fin (preferably <30 nm wide) gated on at least two opposing sides of each of the at least one semiconductor fin. FinFET structures may, for example, typically be formed on either a semiconductor-on-insulator (SOI) substrate or a bulk semiconductor substrate.
A feature of a finFET is a gate electrode located on at least two sides of the channel formed along the longitudinal direction of the fin. Due to the advantageous feature of full depletion in the fin structure, the increased number of sides (e.g., two or three) on which the gate electrode controls the channel of the finFET enhances the controllability of the channel in a finFET compared to a planar MOSFET. The improved control of the channel, among other things, allows smaller device dimensions with less short channel effects as well as larger electrical current that can be switched at high speeds.
Based on, among other things, the characteristics mentioned above, the incorporation of finFET structures within integrated circuits beyond 22 nm nodes (i.e., <22 nm) is becoming more prevalent. While finFET structures provide improved scalability, CMOS technologies may require both active finFET devices (e.g., pFETs and nFETs) and passive devices (e.g., electrostatic discharge diodes, decoupling capacitors, resistors, inductors, etc.) within a single design. However, passive devices usually occupy a substantial area (i.e., real estate) within a semiconductor chip, thus contributing to reducing the device density within the semiconductor chip.